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40m Log |
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Tue Jun 21 21:17:16 2022, yuta, Update, BHD, RTS models for BHD added but PCIE error remaining   
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Wed Jun 22 14:44:03 2022, Anchal, Update, BHD, Fixed DC error in c1su2, added new library model for suspensions
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Tue Jun 28 14:24:23 2022, yuta, Update, BHD, BHD DC PD signals now also sent to c1lsc to circumvent IPC error  
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Mon Nov 14 17:45:02 2022, yuta, Update, BHD, BHD DC PD unwhitening and removing cables to c1lsc
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Mon Nov 21 18:43:46 2022, yuta, Update, BHD, c1hpc and c1lsc modified to send BHD_DIFF and BHD_SUM
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Wed Nov 23 11:06:08 2022, Anchal, Update, BHD, c1hpc and c1sus modified to add BS dither and demodulation option
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Tue Nov 29 15:32:32 2022, Anchal, Update, BHD, c1hpc model updates to support double audio dither
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Tue Dec 6 13:09:44 2022, yuta, Update, BHD, c1cal model updates to support sensing matrix for BHD   
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Message ID: 16938
Entry time: Wed Jun 22 14:44:03 2022
In reply to: 16935
Reply to this: 16954
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Author: |
Anchal |
Type: |
Update |
Category: |
BHD |
Subject: |
Fixed DC error in c1su2, added new library model for suspensions |
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The 0x2000 error in c1su2 happens whenever we make it and install it as the default data acquisition rates are too much in the suspension model. Earlier we used activateSUS2DQ.py to fix this. I followed the suggestion in 40m/16537 to include COIL_OUT at 16k, damping channels at 256 Hz and OL channels at 1024 Hz. I created new suspension model at /cvs/cds/rtcds/userapps/trunk/sus/c1/models/lib/sus_single_control_new.mdl. The model also contains filter modules names C1SUS_OPT_BIASPOS, C1SUS_OPT_BIASPIT, C1SUS_OPT_BIASYAW which acts on the alignment offsets so that a low pass filter can be added there and alignment offsets always happen slowly. The new suspension model is now used inc1su2 for teh 7 new suspensions, and now the model starts without errors.
Still remaining to fix: IPC communication between c1hpc and c1lsc. |