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Entry  Wed Sep 29 17:10:09 2021, Anchal, Summary, CDS, c1teststand problems summary c1teststand_issues_summary.pdf
    Reply  Thu Sep 30 14:09:37 2021, Anchal, Summary, CDS, New way to ssh into c1teststand 
       Reply  Thu Mar 3 15:37:40 2022, Anchal, Summary, CDS, c1teststand restructured 
    Reply  Mon Oct 4 11:05:44 2021, Anchal, Summary, CDS, c1teststand problems summary 
       Reply  Mon Oct 4 18:00:16 2021, Koji, Summary, CDS, c1teststand problems summary 
          Reply  Tue Oct 5 17:58:52 2021, Anchal, Summary, CDS, c1teststand problems summary 
       Reply  Tue Oct 5 18:00:53 2021, Anchal, Summary, CDS, c1teststand time synchronization working now 
          Reply  Mon Oct 11 17:31:25 2021, Anchal, Summary, CDS, Fixed mounting of mx devices in fb. daqd_dc is running now. 
             Reply  Mon Oct 11 18:29:35 2021, Anchal, Summary, CDS, Moving forward? 
                Reply  Tue Oct 12 17:20:12 2021, Anchal, Summary, CDS, Connected c1sus2 to martian network 
                   Reply  Tue Oct 12 23:42:56 2021, Koji, Summary, CDS, Connected c1sus2 to martian network 
                      Reply  Wed Oct 13 11:25:14 2021, Anchal, Summary, CDS, Ran c1sus2 models in martian CDS. All good! CDS_screens_running.png
                         Reply  Tue Oct 19 18:20:33 2021, Ian MacMillan, Summary, CDS, c1sus2 DAC to ADC test data3_Plots.pdfdata2_Plots.pdf
                            Reply  Tue Oct 19 23:43:09 2021, Koji, Summary, CDS, c1sus2 DAC to ADC test P_20211019_224433.jpgP_20211019_224122.jpgP_20211019_224400.jpgP_20211019_224411.jpg
                               Reply  Wed Oct 20 11:48:27 2021, Anchal, Summary, CDS, Power supple configured correctly. 
                               Reply  Tue Oct 26 18:24:00 2021, Ian MacMillan, Summary, CDS, c1sus2 DAC to ADC test data2_Plots.pdfdata3_Plots.pdf
                         Reply  Wed Dec 22 17:40:22 2021, Anchal, Summary, CDS, c1su2 model updated with SUS damping blocks for 7 SOSs 
                            Reply  Wed Dec 29 20:09:40 2021, rana, Summary, CDS, c1su2 model updated with SUS damping blocks for 7 SOSs 
                            Reply  Fri Mar 4 11:04:34 2022, Anchal, Summary, CDS, c1susaux2 system setup and running 40mBHD_C1SUSAUX2_Acromag_Chassis.pdf
                               Reply  Mon Mar 7 19:38:47 2022, Anchal, Summary, CDS, c1susaux2 slow controls issues 
                               Reply  Mon Mar 14 12:20:05 2022, Anchal, Summary, CDS, c1susaux2 slow controls acromag chassis installed BHD_WatchDogs.png40mBHD_C1SUSAUX2_Acromag_Chassis.pdf
                                  Reply  Thu Mar 17 19:12:44 2022, Anchal, Summary, CDS, c1auxey1 slow controls acromag chassis installed, not powered 
                                     Reply  Fri Mar 18 18:39:13 2022, Yehonathan, Summary, CDS, c1auxey1 slow controls acromag chassis installed, powered 
                                        Reply  Fri Mar 18 19:10:51 2022, Anchal, Summary, CDS, c1auxey1 slow controls issues 
                                           Reply  Mon Mar 21 18:42:06 2022, Anchal, Summary, CDS, c1auxey1 slow controls issues 
                                  Reply  Mon Apr 4 17:03:47 2022, Anchal, Summary, CDS, c1susaux2 slow controls acromag chassis fixed and installed Screenshot_2022-04-04_17-03-26.png
                            Reply  Tue Mar 15 11:52:34 2022, Anchal, Summary, CDS, c1su2 model updated for sending Run/Acquire Binary Output to Binary Interface card c1su2.pdf
                               Reply  Tue Mar 15 14:10:41 2022, Anchal, Summary, CDS, c1su2 model remade, reinstalled, restarted after the update 
             Reply  Tue Oct 12 17:10:56 2021, Anchal, Summary, CDS, Some more information 
Message ID: 16414     Entry time: Tue Oct 19 18:20:33 2021     In reply to: 16398     Reply to this: 16415
Author: Ian MacMillan 
Type: Summary 
Category: CDS 
Subject: c1sus2 DAC to ADC test 

I ran a DAC to ADC test on c1sus2 channels where I hooked up the outputs on the DAC to the input channels on the ADC. We used different combinations of ADCs and DACs to make sure that there were no errors that cancel each other out in the end. I took a transfer function across these channel combinations to reproduce figure 1 in T2000188.

As seen in the two attached PDFs the channels seem to be working properly they have a flat response with a gain of 0.5 (-6 dB). This is the response that is expected and is the result of the DAC signal being sent as a single ended signal and the ADC receiving as a differential input signal. This should result in a recorded signal of 0.5 the amplitude of the actual output signal.

The drop off on the high frequency end is the result of the anti-aliasing filter and the anti-imaging filter. Both of these are 8-pole elliptical filters so when combined we should get a drop off of 320dB per decade. I measured the slope on the last few points of each filter and the averaged value was around 347dB per decade. This is slightly steeper than expected but since it is to cut off higher frequencies it shouldn't have an effect on the operation of the system. Also it is very close to the expected value.

The ripples seen before the drop off are also an effect of the elliptical filters and are seen in T2000188.

Note: the transfer function that doesn't seem to match the others is the heartbeat timing signal.

Attachment 1: data3_Plots.pdf  154 kB  Uploaded Tue Oct 19 19:39:53 2021  | Hide | Hide all
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Attachment 2: data2_Plots.pdf  171 kB  Uploaded Tue Oct 19 19:41:26 2021  | Hide | Hide all
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