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Entry  Wed Feb 24 22:13:47 2021, Jon, Update, CDS, Planning document for front-end testing 
    Reply  Fri Mar 5 17:48:25 2021, Jon, Update, CDS, Front-end testing image_67203585.JPGimage_67216641.JPGimage_17185537.JPG
       Reply  Tue Mar 9 16:52:47 2021, Jon, Update, CDS, Front-end testing image_72192707.JPG
          Reply  Tue Mar 16 16:27:22 2021, Jon, Update, CDS, Front-end testing 
             Reply  Tue Mar 16 19:04:20 2021, gautam, Update, CDS, Front-end testing 
             Reply  Fri Mar 19 18:14:56 2021, Jon, Update, CDS, Front-end testing image_72192707_(1).JPGimage_50412545.JPG
                Reply  Wed Mar 24 19:02:21 2021, Jon, Update, CDS, Front-end testing 
                   Reply  Mon Mar 29 17:55:50 2021, Jon, Update, CDS, Front-end testing 
                      Reply  Tue Mar 30 18:21:34 2021, Jon, Update, CDS, Front-end testing 
                      Reply  Tue Apr 6 07:19:11 2021, Jon, Update, CDS, New SimPlant cymac 
                         Reply  Tue Apr 6 11:13:01 2021, Jon, Update, CDS, FE testing 
                            Reply  Sat Apr 10 08:51:32 2021, Jon, Update, CDS, I/O Chassis Assembly 
                               Reply  Thu Apr 29 10:51:35 2021, Jon, Update, CDS, I/O Chassis Assembly 
                                  Reply  Tue May 4 07:38:36 2021, Jon, Update, CDS, I/O Chassis Assembly Screen_Shot_2021-05-03_at_4.16.06_PM.png
                                     Reply  Tue May 11 16:29:55 2021, Jon, Update, CDS, I/O Chassis Assembly Screen_Shot_2021-05-11_at_3.03.42_PM.png
                                        Reply  Tue May 11 17:43:09 2021, Koji, Update, CDS, I/O Chassis Assembly 
                                           Reply  Fri May 28 11:16:21 2021, Jon, Update, CDS, Front-End Assembly and Testing c1bhd.pnggds_tp.pngteststand.jpegbench_supply.jpeg
                                              Reply  Sun Jun 6 08:42:05 2021, Jon, Update, CDS, Front-End Assembly and Testing c1bhd.png16bit_dacs.pngmyricom.png
                                                 Reply  Tue Jun 22 16:53:01 2021, Ian MacMillan, Update, CDS, Front-End Assembly and Testing 
                                                    Reply  Thu Jun 24 17:32:52 2021, Ian MacMillan, Update, CDS, Front-End Assembly and Testing C1-SU2_Channel_Responses.pdfC1-BHD_Channel_Responses.pdfCDS_Channel_Test.zip
                                                       Reply  Fri Jun 25 14:06:10 2021, Jon, Update, CDS, Front-End Assembly and Testing test_stand.JPG
Message ID: 16225     Entry time: Fri Jun 25 14:06:10 2021     In reply to: 16224
Author: Jon 
Type: Update 
Category: CDS 
Subject: Front-End Assembly and Testing 

Summary

Here is the final summary (from me) of where things stand with the new front-end systems. With Anchal and Ian's recent scripted loopback testing [16224], all the testing that can be performed in isolation with the hardware on hand has been completed. We currently have no indication of any problem with the new hardware. However, the high-frequency signal integrity and noise testing remains to be done.

I detail those tests and link some DTT templates for performing them below. We have not yet received the Myricom 10G network card being sent from LHO, which is required to complete the standalone DAQ network. Thus we do not have a working NDS server in the test stand, so cannot yet run any of the usual CDS tools such as Diaggui. Another option would be to just connect the new front-ends to the 40m Martian/DAQ networks and test them there.

Final Hardware Configuration

Due to the unavailablity of the 18-bit DACs that were expected from the sites, we elected to convert all the new 18-bit AO channels to 16-bit. I was able to locate four unused 16-bit DACs around the 40m [16185], with three of the four found to be working. I was also able to obtain three spare 16-bit DAC adapter boards from Todd Etzel. With the addition of the three working DACs, we ended up with just enough hardware to complete both systems.

The final configuration of each I/O chassis is as follows. The full setup is pictured in Attachment 1.

  C1BHD C1SUS2
Component Qty Installed Qty Installed
16-bit ADC 1 2
16-bit ADC adapter 1 2
16-bit DAC 1 3
16-bit DAC adapter 1 3
16-channel BIO 1 1
32-channel BO 0 6

This hardware provides the following breakdown of channels available to user models:

  C1BHD C1SUS2
Channel Type Channel Count Channel Count
16-bit AI* 31 63
16-bit AO 16 48
BO 0 192

*The last channel of the first ADC is reserved for timing diagnostics.

The chassis have been closed up and their permanent signal cabling installed. They do not need to be reopened, unless future testing finds a problem.

RCG Model Configuration

An IOP model has been created for each system reflecting its final hardware configuration. The IOP models are permanent and system-specific. When ready to install the new systems, the IOP models should be copied to the 40m network drive and installed following the RCG-compilation procedure in [15979]. Each system also has one temporary user model which was set up for testing purposes. These user models will be replaced with the actual SUS, OMC, and BHD models when the new systems are installed.

The current RCG models and the action to take with each one are listed below:

Model Name Host CPU DCUID Path (all paths local to chiara clone machine) Action
c1x06 c1bhd 1 23 /opt/rtcds/userapps/release/cds/c1/models/c1x06.mdl Copy to same location on 40m network drive; compile and install
c1x07 c1sus2 1 24 /opt/rtcds/userapps/release/cds/c1/models/c1x07.mdl Copy to same location on 40m network drive; compile and install
c1bhd c1bhd 2 25 /opt/rtcds/userapps/release/isc/c1/models/c1bhd.mdl Do not copy; replace with permanent OMC/BHD model(s)
c1su2 c1su2 2 26 /opt/rtcds/userapps/release/sus/c1/models/c1su2.mdl Do not copy; replace with permanent SUS model(s)

Each front-end can support up to four user models.

Future Signal-Integrity Testing

Recently, the CDS group has released a well-documented procedure for testing General Standards ADC and DACs: T2000188. They've also automated the tests using a related set of shell scripts (T2000203). Unfortnately I don't believe these scripts will work at the 40m, as they require the latest v4.x RCG.

However, there is an accompanying set of DTT templates that could be very useful for accelerating the testing. They are available from the LIGO SVN (log in with username: "first.last@LIGO.ORG"). I believe these can be used almost directly, with only minor updates to channel names, etc. There are two classes of DTT-templated tests:

  1. DAC -> ADC loopback transfer functions
  2. Voltage noise floor PSD measurements of individual cards

The T2000188 document contains images of normal/passing DTT measurements, as well as known abnormalities and failure modes. More sophisticated tests could also be configured, using these templates as a guiding example.

Hardware Reordering

Due to the unexpected change from 18- to 16-bit AO, we are now short on several pieces of hardware:

  • 16-bit AI chassis. We originally ordered five of these chassis, and all are obligated as replacements within the existing system. Four of them are now (temporarily) in use in the front-end test stand. Thus four of the new 18-bit AI chassis will need to be retrofitted with 16-bit hardware.
  • 16-bit DACs. We currently have exactly enough DACs. I have requested a quote from General Standards for two additional units to have as spares.
  • 16-bit DAC adapters. I have asked Todd Etzel for two additional adapter boards to also have as spares. If no more are available, a few more should be fabricated.
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