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Entry  Wed Feb 24 22:13:47 2021, Jon, Update, CDS, Planning document for front-end testing 
    Reply  Fri Mar 5 17:48:25 2021, Jon, Update, CDS, Front-end testing image_67203585.JPGimage_67216641.JPGimage_17185537.JPG
       Reply  Tue Mar 9 16:52:47 2021, Jon, Update, CDS, Front-end testing image_72192707.JPG
          Reply  Tue Mar 16 16:27:22 2021, Jon, Update, CDS, Front-end testing 
             Reply  Tue Mar 16 19:04:20 2021, gautam, Update, CDS, Front-end testing 
             Reply  Fri Mar 19 18:14:56 2021, Jon, Update, CDS, Front-end testing image_72192707_(1).JPGimage_50412545.JPG
                Reply  Wed Mar 24 19:02:21 2021, Jon, Update, CDS, Front-end testing 
                   Reply  Mon Mar 29 17:55:50 2021, Jon, Update, CDS, Front-end testing 
                      Reply  Tue Mar 30 18:21:34 2021, Jon, Update, CDS, Front-end testing 
                      Reply  Tue Apr 6 07:19:11 2021, Jon, Update, CDS, New SimPlant cymac 
                         Reply  Tue Apr 6 11:13:01 2021, Jon, Update, CDS, FE testing 
                            Reply  Sat Apr 10 08:51:32 2021, Jon, Update, CDS, I/O Chassis Assembly 
                               Reply  Thu Apr 29 10:51:35 2021, Jon, Update, CDS, I/O Chassis Assembly 
                                  Reply  Tue May 4 07:38:36 2021, Jon, Update, CDS, I/O Chassis Assembly Screen_Shot_2021-05-03_at_4.16.06_PM.png
                                     Reply  Tue May 11 16:29:55 2021, Jon, Update, CDS, I/O Chassis Assembly Screen_Shot_2021-05-11_at_3.03.42_PM.png
                                        Reply  Tue May 11 17:43:09 2021, Koji, Update, CDS, I/O Chassis Assembly 
                                           Reply  Fri May 28 11:16:21 2021, Jon, Update, CDS, Front-End Assembly and Testing c1bhd.pnggds_tp.pngteststand.jpegbench_supply.jpeg
                                              Reply  Sun Jun 6 08:42:05 2021, Jon, Update, CDS, Front-End Assembly and Testing c1bhd.png16bit_dacs.pngmyricom.png
                                                 Reply  Tue Jun 22 16:53:01 2021, Ian MacMillan, Update, CDS, Front-End Assembly and Testing 
                                                    Reply  Thu Jun 24 17:32:52 2021, Ian MacMillan, Update, CDS, Front-End Assembly and Testing C1-SU2_Channel_Responses.pdfC1-BHD_Channel_Responses.pdfCDS_Channel_Test.zip
                                                       Reply  Fri Jun 25 14:06:10 2021, Jon, Update, CDS, Front-End Assembly and Testing test_stand.JPG
Message ID: 16130     Entry time: Tue May 11 16:29:55 2021     In reply to: 16116     Reply to this: 16131
Author: Jon 
Type: Update 
Category: CDS 
Subject: I/O Chassis Assembly 
Quote:

Timing system set-up

The next step is to provide the 65 kHz clock signals from the timing fanout via LC optical fiber. I overlooked the fact that an SPX optical transceiver is required to interface the fiber to the timing slave board. These were not provided with the timing slaves we received. The timing slaves require a particular type of transceiver, 100base-FX/OC-3, which we did not have on hand. (For future reference, there is a handy list of compatible transceivers in E080541, p. 14.) I placed a Digikey order for two Finisar FTLF1217P2BTL, which should arrive within two days.

Today I brought and installed the new optical transceivers (Finisar FTLF1217P2BTL) for the two timing slaves. The timing slaves appear to phase-lock to the clocking signal from the master fanout. A few seconds after each timing slave is powered on, its status LED begins steadily blinking at 1 Hz, just as in the existing 40m systems.

However, some other timing issue remains unresolved. When the IOP model is started (on either FE), the DACKILL watchdog appears to start in a tripped state. Then after a few minutes of running, the TIM and ADC indicators go down as well. This makes me suspect the sample clocks are not really phase-locked. However, the models do start up with no error messages. Will continue to debug...

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