Some short notes, more details tomorrow.

1. I was able to make it to CARM on RF only ~10 times tonight.
2. Highest stable circulating power was ~200 (recycling gain ~10) but the control scheme is still not finalized in terms of offsets etc.
3. DARM to RF transition was never fully engaged - I got to a point where the ALS gain was reduced to <half its nominal value, but IMC always lost lock.
4. CARM loop UGF of ~5 kHz was realized. I was also able to turn on a regular boost. But couldn't push the gain up much more than this. Should probably modify the boosts on this board, their corner frequencies are pretty high.
5. The increased FSS flakiness post c1psl upgrade is definitely hurting this effort, there are periods of ~20-30mins when the IMC just wont lock.

Attachment #1 shows time series of some signals, from the time I ramp of ALS CARM control to a lockloss. With this limited set of signals, I don't see any clear indication of the cause of lockloss, but I was never able to keep the lock going for > a couple of mins.

Attachment #2 shows the CARM OLTF. Compared to last week, I was able to get the UGF a little higher. This particular measurement doesn't show it, but I was also able to engage the regular boost. I did a zeroth order test looking at the CM_SLOW input to make sure that I wasn't increasing the gain so much that the ADC was getting saturated. However, I did notice that the pk-to-pk error signal in this locked, 5kHz UGF state was still ~1000 cts, which seems large?

Attachment #3 shows the DTT measurement of the relative gains of DARM A and B paths. This measurement was taken when the DARM_A gain was 1, and DARM_B gain was 0.015. On the basis of this measurement, DARM_B (=AS55) sees the excitation injected 16dB above the ALS signal, and so the gain of the DARM_B path should be ~0.16 for the same UGF. But I was never able to get the DARM_B gain above 0.02 without breaking the lock (admittedly the lockloss may have been due to something else).

Attachment #4 shows a zoomed in version of Attachment #1 around the time when the lock was lost. Maybe POP_YAW experienced too large an excursion?

Some other misc points:

• It was much quicker to acquire the PRMI lock with CARM held off resonance using the 1f signals rather than 3f - so I did that and then once the lock is acquired, transfer control to 3f signals (using CDS ramptime) before zeroing the CARM offset.
• The whole process is pretty speedy - it takes <5mins to get to the CARM on RF only stage provided the PRMI lock doesn't take too long (the transition from POX/POY to ALS sequence takes <1min).
• I am wondering what the correct way to set the offsets for the 3f error signals is? 
• The arm buildup is strongly dependent on the DC alignment of the PRMI - the best buildups I got were when I tweaked the BS alignment after the CARM offset was zeroed.