40m QIL Cryo_Lab CTN SUS_Lab TCS_Lab OMC_Lab CRIME_Lab FEA ENG_Labs OptContFac Mariner WBEEShop
  40m Log  Not logged in ELOG logo
Entry  Fri Sep 20 12:55:02 2019, gautam, Update, CDS, c1iscaux testing 
    Reply  Mon Sep 23 10:49:34 2019, rana, Update, CDS, c1iscaux testing 
    Reply  Wed Sep 25 20:10:13 2019, Koji, Update, CDS, c1iscaux testing testDetectMons_190925.pngtestIPPOS_190925.png
       Reply  Thu Sep 26 20:09:40 2019, Koji, Update, CDS, c1iscaux testing Wht1.pdfWht2.pdfWht3.pdfWht4.pdflock.png
          Reply  Fri Sep 27 15:59:53 2019, gautam, Update, CDS, c1iscaux testing 
          Reply  Wed Oct 2 01:11:40 2019, Koji, Update, CDS, c1iscaux testing 8x
             Reply  Fri Oct 4 01:57:09 2019, Koji, Update, CDS, c1iscaux testing P_20191003_172956_vHDR_On.jpgTF.pdfPSD.pdf191003_AA_Filter.zip
                Reply  Sat Oct 5 00:03:21 2019, Koji, Update, CDS, c1iscaux testing REFL1_GAIN1.pdfREFL1_GAIN2.pdfREFL2_GAIN1.pdfREFL2_GAIN2.pdf
                   Reply  Tue Oct 8 03:32:42 2019, Koji, Update, CDS, CM servo board testing 7x
                      Reply  Tue Oct 8 17:59:29 2019, Koji, Update, CDS, CM servo board testing (portal) 6x
                         Reply  Tue Oct 8 18:42:39 2019, Koji, Update, CDS, CM servo board testing boosts.pdf
                            Reply  Mon Oct 14 16:06:28 2019, Koji, Update, CDS, CM servo board testing pole_zero_filter.pdf
                               Reply  Mon Oct 14 16:19:30 2019, Koji, Update, CDS, CM servo board testing testb2.pdf
                                  Reply  Mon Oct 14 16:25:03 2019, Koji, Update, CDS, CM servo board testing servo_out.pdf
                                     Reply  Mon Oct 14 16:34:42 2019, Koji, Update, CDS, CM servo board testing in12_output_offset.pdfin12_input_offset.pdfin12_input_offset2.pdf
                                        Reply  Mon Oct 14 17:32:28 2019, Koji, Update, CDS, Portal Elog entry for the recent CM servo board tests CM_Servo_Diagram.png
                         Reply  Tue Oct 8 20:23:03 2019, gautam, Update, CDS, c1iscaux testing 
    Reply  Mon Sep 30 11:20:43 2019, gautam, Update, CDS, c1iscaux testing - CM board code updated CMsoftTest.png
       Reply  Mon Sep 30 15:51:59 2019, gautam, Update, CDS, c1iscaux - some admin 
Message ID: 14942     Entry time: Sat Oct 5 00:03:21 2019     In reply to: 14939     Reply to this: 14948
Author: Koji 
Type: Update 
Category: CDS 
Subject: c1iscaux testing 

[Gautam, Koji]

Input gain part of the CM servo board D1500308 was tested. A couple of problems were detected. One still remains.

== Test Status ==

[done] Whitening gain switching test
[done] AA enable/disable switching
[0th order] LO Det Mon channel check
[none] PD I/F board check
[done] QPD I/F board check
[in progress] CM Board
[none] ALS I/F board

We started to test the CM Servo board from the input stages. Initially, DC offsets were provided to IN1 and IN2 to check the gain on the oscilloscope or a StripTool plot. However, the results were confusing, AC measurements with SR785 was carried out in the end. It turned out that both IN1 and IN2 had some issues. IN1 showed an increment of the gain by 2dB every two gain steps, having suggested that the 1dB gain stage had a problem. IN2 showed sudden drop of the signal at the gain +8~+15dB and +24~+31dB, having suggested that a particular 8dB stage had a problem. The board was exposed with the extender and started tracing the signals.

CH1: The digital signal to switch the 1dB stage reached Pin 1A of the DIN96 connector. However, the latch logic (U47 74ALS573) does not spit out the corresponding level for this bit. Note that the next bit was properly working. We concluded that this 74ALS573 had failed and need to be replaced. We have no spare of this wide SOIC-20 chip, but Downs seems to have some spares (see Todd's spare parts list). We will try to get the chip on Monday.

CH2: The stage only used between +8dB and +15dB and between +24dB and +31dB is the +8dB stage (U9 and U2A). I found that the amped output signal did not reach the FET switch U2A (MAX333A). Therefore it was concluded that the opamp U9 (AD829) has an issue. In fact, the amp itself was working, but the output pin was not properly soldered to the pad.  Resoldering this chip made the issue gone. Note that this particular channel has some OP27s soldered instead of AD829. Gautam mentioned that there was some action on the board a few years back to deal with the offset issue. Next time when the board is polled out, I'll take the photos of the board.

Using SR785, the swept sine measurements between 100 and 100kHz were taken for all the gain settings for each channel. Between -31dB and -11dB, the input signal amplitude of 300mV was used. Between -10dB and +10dB, it was reduced to 100mV. For the rest, the amplitude was 10mV. Note that the data for +11dB for CH1 and +2dB for CH2 are missing presumably due to a data transfer issue.

The results are shown in Attachments 1~4.

Attachments 1 and 3 show the gain at each slider value. The measured gain was represented by the average between 1kHz and 10kHz. The missing 1dB every two slide values are seen for CH1. The phase delay at 100kHz is show in the lower plot. There is some delay and delay variation seen but it is in fact less than 1deg at 10kHz (see later) so it's effectfor CM servo (IMC AO path) is minimum. The gain for CH2 tracks the slider value nicely. The phase delay is larger than that of CH1, as expected because of OP27.

Attachments 2 and 4 show the transfer functions. The slider value was subtracted from the measured gain magnitude to indicate the deviation between them. The missing 1dB is obviously visible for CH1 in addition to the overall gain offset of ~0.2dB. CH2 also shows the gain offset of 0.1dB~0.2dB. The phase delay comes into the play around 20kHz particularly at higher gains where the UGF of the AO path is.

gautam: Here is the elog thread for IN2 opAmps going AD829-->OP27. Also, I guess Attachment #1 and #3 x-axes should be "Gain [dB]" rather than "Frequency [Hz]".

Attachment 1: REFL1_GAIN1.pdf  133 kB  Uploaded Sat Oct 5 14:34:44 2019  | Hide | Hide all
Attachment 2: REFL1_GAIN2.pdf  277 kB  Uploaded Sat Oct 5 14:36:23 2019  | Hide | Hide all
Attachment 3: REFL2_GAIN1.pdf  133 kB  Uploaded Sat Oct 5 14:36:23 2019  | Hide | Hide all
Attachment 4: REFL2_GAIN2.pdf  306 kB  Uploaded Sat Oct 5 14:36:23 2019  | Hide | Hide all
ELOG V3.1.3-