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Entry  Fri Sep 20 12:55:02 2019, gautam, Update, CDS, c1iscaux testing 
    Reply  Mon Sep 23 10:49:34 2019, rana, Update, CDS, c1iscaux testing 
    Reply  Wed Sep 25 20:10:13 2019, Koji, Update, CDS, c1iscaux testing testDetectMons_190925.pngtestIPPOS_190925.png
       Reply  Thu Sep 26 20:09:40 2019, Koji, Update, CDS, c1iscaux testing Wht1.pdfWht2.pdfWht3.pdfWht4.pdflock.png
          Reply  Fri Sep 27 15:59:53 2019, gautam, Update, CDS, c1iscaux testing 
          Reply  Wed Oct 2 01:11:40 2019, Koji, Update, CDS, c1iscaux testing 8x
             Reply  Fri Oct 4 01:57:09 2019, Koji, Update, CDS, c1iscaux testing P_20191003_172956_vHDR_On.jpgTF.pdfPSD.pdf191003_AA_Filter.zip
                Reply  Sat Oct 5 00:03:21 2019, Koji, Update, CDS, c1iscaux testing REFL1_GAIN1.pdfREFL1_GAIN2.pdfREFL2_GAIN1.pdfREFL2_GAIN2.pdf
                   Reply  Tue Oct 8 03:32:42 2019, Koji, Update, CDS, CM servo board testing 7x
                      Reply  Tue Oct 8 17:59:29 2019, Koji, Update, CDS, CM servo board testing (portal) 6x
                         Reply  Tue Oct 8 18:42:39 2019, Koji, Update, CDS, CM servo board testing boosts.pdf
                            Reply  Mon Oct 14 16:06:28 2019, Koji, Update, CDS, CM servo board testing pole_zero_filter.pdf
                               Reply  Mon Oct 14 16:19:30 2019, Koji, Update, CDS, CM servo board testing testb2.pdf
                                  Reply  Mon Oct 14 16:25:03 2019, Koji, Update, CDS, CM servo board testing servo_out.pdf
                                     Reply  Mon Oct 14 16:34:42 2019, Koji, Update, CDS, CM servo board testing in12_output_offset.pdfin12_input_offset.pdfin12_input_offset2.pdf
                                        Reply  Mon Oct 14 17:32:28 2019, Koji, Update, CDS, Portal Elog entry for the recent CM servo board tests CM_Servo_Diagram.png
                         Reply  Tue Oct 8 20:23:03 2019, gautam, Update, CDS, c1iscaux testing 
    Reply  Mon Sep 30 11:20:43 2019, gautam, Update, CDS, c1iscaux testing - CM board code updated CMsoftTest.png
       Reply  Mon Sep 30 15:51:59 2019, gautam, Update, CDS, c1iscaux - some admin 
Message ID: 14939     Entry time: Fri Oct 4 01:57:09 2019     In reply to: 14921     Reply to this: 14942
Author: Koji 
Type: Update 
Category: CDS 
Subject: c1iscaux testing 

The AA filter for ASDC was fixed.

== Test Status ==

[done] Whitening gain switching test
[done] AA enable/disable switching
[0th order] LO Det Mon channel check
[none] PD I/F board check
[done] QPD I/F board check
[none] CM Board
[none] ALS I/F board


The AA filter for the 4th section of the LSC analog electronics bank (D000076) was pulled out for the test. On the workbench, questionable CH8 was checked. It tuned out that the filter amplifier module for the 8th-order elliptic filter at 7.5kHz was not properly working and exhibited unusual attenuation. This filter module (Frequency Devices Inc D68L8E-7.50kHz) was desoldered and replaced with a module from a spare board. Note that Gautam and I had tried to use this spare board instead of the current one, but it didn't give us any signal for an unknown reason. Since the desoldering required a lot of force and had a risk of damaging the PCB, a socket was made from an IC socket (see Attached 1). This change made CH8 functioning equally to the other channels do.


I took this opportunity to ckech the performance of the AA filters. For each channel, the input signal was injected from J3 using a pomona clip. The output was taken from pin 1, 5, 9, ... of J2. This is the + side of the differential output. The - side just has the equivalent performance but the signal polarity. The digital signals for the AA bypass switches were not connected. Fortunately, this was just fine as it made the anti-aliasing filters engaged.

Attachment 2 shows the transfer functions of all the channels. All the channels showed an identical response (at least visually). The transfer function for CH1 was fitted by LISO. The ZPK values are listed here:

pole 5.2860544577k 503.1473053928m
pole 5.9752193716k 1.0543411596
pole 8.9271953580k 3.5384364788
pole 8.2181747850k 3.4220607928
pole 182.1403534923k 1.1187869426 # This has almost no effect
zero 13.5305051680k 423.6130434049M
zero 15.5318357741k 747.6895990654k
zero 23.1746351749k 1.5412966100M


factor 989.1003181564m
delay 24.4846075283n

Attachment 3 shows the ASD of the output voltage noise measurement. Note the input was shorted for this measurement. The nominal output voltage was found to be 0.1 uV/rtHz and the 1/f noise corner freq was about 100Hz. Only CH3 showed a deviation from the typical values. It looks like this is neither an artifact nor transient noise. Fortunately, nothing is connected to this channel right now.

Attachment 1: P_20191003_172956_vHDR_On.jpg  831 kB  Uploaded Fri Oct 4 03:11:46 2019  | Hide | Hide all
P_20191003_172956_vHDR_On.jpg
Attachment 2: TF.pdf  138 kB  Uploaded Fri Oct 4 13:26:17 2019  | Hide | Hide all
TF.pdf
Attachment 3: PSD.pdf  345 kB  Uploaded Fri Oct 4 13:26:25 2019  | Hide | Hide all
PSD.pdf
Attachment 4: 191003_AA_Filter.zip  1.793 MB  Uploaded Fri Oct 4 13:37:27 2019
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