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Entry  Fri Sep 20 12:55:02 2019, gautam, Update, CDS, c1iscaux testing 
    Reply  Mon Sep 23 10:49:34 2019, rana, Update, CDS, c1iscaux testing 
    Reply  Wed Sep 25 20:10:13 2019, Koji, Update, CDS, c1iscaux testing testDetectMons_190925.pngtestIPPOS_190925.png
       Reply  Thu Sep 26 20:09:40 2019, Koji, Update, CDS, c1iscaux testing Wht1.pdfWht2.pdfWht3.pdfWht4.pdflock.png
          Reply  Fri Sep 27 15:59:53 2019, gautam, Update, CDS, c1iscaux testing 
          Reply  Wed Oct 2 01:11:40 2019, Koji, Update, CDS, c1iscaux testing 8x
             Reply  Fri Oct 4 01:57:09 2019, Koji, Update, CDS, c1iscaux testing P_20191003_172956_vHDR_On.jpgTF.pdfPSD.pdf191003_AA_Filter.zip
                Reply  Sat Oct 5 00:03:21 2019, Koji, Update, CDS, c1iscaux testing REFL1_GAIN1.pdfREFL1_GAIN2.pdfREFL2_GAIN1.pdfREFL2_GAIN2.pdf
                   Reply  Tue Oct 8 03:32:42 2019, Koji, Update, CDS, CM servo board testing 7x
                      Reply  Tue Oct 8 17:59:29 2019, Koji, Update, CDS, CM servo board testing (portal) 6x
                         Reply  Tue Oct 8 18:42:39 2019, Koji, Update, CDS, CM servo board testing boosts.pdf
                            Reply  Mon Oct 14 16:06:28 2019, Koji, Update, CDS, CM servo board testing pole_zero_filter.pdf
                               Reply  Mon Oct 14 16:19:30 2019, Koji, Update, CDS, CM servo board testing testb2.pdf
                                  Reply  Mon Oct 14 16:25:03 2019, Koji, Update, CDS, CM servo board testing servo_out.pdf
                                     Reply  Mon Oct 14 16:34:42 2019, Koji, Update, CDS, CM servo board testing in12_output_offset.pdfin12_input_offset.pdfin12_input_offset2.pdf
                                        Reply  Mon Oct 14 17:32:28 2019, Koji, Update, CDS, Portal Elog entry for the recent CM servo board tests CM_Servo_Diagram.png
                         Reply  Tue Oct 8 20:23:03 2019, gautam, Update, CDS, c1iscaux testing 
    Reply  Mon Sep 30 11:20:43 2019, gautam, Update, CDS, c1iscaux testing - CM board code updated CMsoftTest.png
       Reply  Mon Sep 30 15:51:59 2019, gautam, Update, CDS, c1iscaux - some admin 
Message ID: 14912     Entry time: Mon Sep 30 11:20:43 2019     In reply to: 14903     Reply to this: 14916
Author: gautam 
Type: Update 
Category: CDS 
Subject: c1iscaux testing - CM board code updated 

DATED, SEE ELOG14941 for the most up-to-date info on latch.py.

I modified /cvs/cds/caltech/target/c1iscaux/latch.py and /cvs/cds/caltech/target/c1iscaux/C1_ISC-AUX_CM.db to set up the mbbo logic for the other three channels on the CM board, namely REFL2 Gain, AO Gain, and the Super boosts. The systemctl processes were restarted on c1iscaux. We are now ready to perform systematic checks on the CM board functionality.

Remarks:

The addressing of the Acromag BIO registers is done in a way that is kind of inconvenient to use the EPICS mbboDirect protocol

  • The control word going to the Acromag is 16 bits in length
  • However, only the 4 least significant bits actually correspond to physical channels - the remaining 12 bits are "unused".
  • Because each Acromag BIO unit has 16 BIO channels, this means that they are grouped into four "banks" of 4 bits each.
  • The mbboDirect EPICS/modbus protocol is used to control multiple physical BIO channels using a single input, which is exactly what we want for the gain sliders on the CM board. However, one caveat is that the bits need to be consecutive.
  • This means that we have to break up the 6 bits used for the gain sliders (and in fact also the 2 bits used for the super boosts) into a least-significant-bits (LSB) group and a most-significant-bits (MSB) group.
  • What's more annoying is that our physical wiring scheme means that we can't uniformly decide on how this division into LSBs and MSBs work for all the channels - e.g. for REFL1 Gain, the LSB is the 4 least significant bits, while the MSB is the 2 most significant ones, while for REFL2 Gain, the roles are reversed.
  • In hindsight, the "clever" way to do the wiring assignment would have been to factor this in - but the problem is (sort of) easily fixed in software, and so I recommend we stick with the existing wiring scheme.

I tested the new latch.py script by toggling the various sliders (one at a time) between two values and monitoring the states of the various soft and "*_BITS" channels, see Attachment #1. The behavior seems consistent to me, but to be sure, we have to use Koji's LED tester board and confirm that the physical bits are being toggled correctly. The StripTool templates live in /cvs/cds/caltech/target/c1iscaux/CMdiag.

Quote:

I have not yet implemented the fix for the MBBO gain channels for all the gains - only REFL1_GAIN is set up correctly now. Need to look at the hardware for the correct addressing of bits

Attachment 1: CMsoftTest.png  52 kB  Uploaded Mon Sep 30 13:30:20 2019  | Hide | Hide all
CMsoftTest.png
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