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Entry  Fri Sep 20 12:55:02 2019, gautam, Update, CDS, c1iscaux testing 
    Reply  Mon Sep 23 10:49:34 2019, rana, Update, CDS, c1iscaux testing 
    Reply  Wed Sep 25 20:10:13 2019, Koji, Update, CDS, c1iscaux testing testDetectMons_190925.pngtestIPPOS_190925.png
       Reply  Thu Sep 26 20:09:40 2019, Koji, Update, CDS, c1iscaux testing Wht1.pdfWht2.pdfWht3.pdfWht4.pdflock.png
          Reply  Fri Sep 27 15:59:53 2019, gautam, Update, CDS, c1iscaux testing 
          Reply  Wed Oct 2 01:11:40 2019, Koji, Update, CDS, c1iscaux testing 8x
             Reply  Fri Oct 4 01:57:09 2019, Koji, Update, CDS, c1iscaux testing P_20191003_172956_vHDR_On.jpgTF.pdfPSD.pdf191003_AA_Filter.zip
                Reply  Sat Oct 5 00:03:21 2019, Koji, Update, CDS, c1iscaux testing REFL1_GAIN1.pdfREFL1_GAIN2.pdfREFL2_GAIN1.pdfREFL2_GAIN2.pdf
                   Reply  Tue Oct 8 03:32:42 2019, Koji, Update, CDS, CM servo board testing 7x
                      Reply  Tue Oct 8 17:59:29 2019, Koji, Update, CDS, CM servo board testing (portal) 6x
                         Reply  Tue Oct 8 18:42:39 2019, Koji, Update, CDS, CM servo board testing boosts.pdf
                            Reply  Mon Oct 14 16:06:28 2019, Koji, Update, CDS, CM servo board testing pole_zero_filter.pdf
                               Reply  Mon Oct 14 16:19:30 2019, Koji, Update, CDS, CM servo board testing testb2.pdf
                                  Reply  Mon Oct 14 16:25:03 2019, Koji, Update, CDS, CM servo board testing servo_out.pdf
                                     Reply  Mon Oct 14 16:34:42 2019, Koji, Update, CDS, CM servo board testing in12_output_offset.pdfin12_input_offset.pdfin12_input_offset2.pdf
                                        Reply  Mon Oct 14 17:32:28 2019, Koji, Update, CDS, Portal Elog entry for the recent CM servo board tests CM_Servo_Diagram.png
                         Reply  Tue Oct 8 20:23:03 2019, gautam, Update, CDS, c1iscaux testing 
    Reply  Mon Sep 30 11:20:43 2019, gautam, Update, CDS, c1iscaux testing - CM board code updated CMsoftTest.png
       Reply  Mon Sep 30 15:51:59 2019, gautam, Update, CDS, c1iscaux - some admin 
Message ID: 14908     Entry time: Thu Sep 26 20:09:40 2019     In reply to: 14906     Reply to this: 14909   14921
Author: Koji 
Type: Update 
Category: CDS 
Subject: c1iscaux testing 

== Test Status ==

[done] Whitening gain switching test => Some issues found (POP110Q, Whitening3_8 not switching, ASDC overall behavior, REFL33Q needs recheck)
[done] AA enable/disable switching
[0th order] LO Det Mon channel check
[none] PD I/F board check
[done] QPD I/F board check
[none] CM Board
[none] ALS I/F board

And, the Y-arm lock was recovered! After some alignment work, the Y-arm was locked. The whitening gain for POY11 was +18dB. The servo gain was 0.015 (nominal).
Once the transmission reached 0.8, I could use ASS to align the cavity and the TTs.
The transmission reached just 1.00 at the end. Was the transmission recently normalized? (See attachment 5)


- Whitening Filter Gain Switching Test

Each whitening filters were tested individually. +50mV DC signal was connected to the 8 inputs using an SMA octopus cable.
The existing script ( /cvs/cds/caltech/target/c1iscaux/testScripts/testWhtGain.py ) did not work because cds.getdata failed to fetch all of the data requested. By giving some sleep before start downloading the data, the problem was avoided. Still some truncated data are seen in the result, but StripTools screenshots compliments the missing part.

Whitening Filters #2~4 were a little tricky because the code needed modification so that the spare channels can be tested.
The modified script is stored as /cvs/cds/caltech/target/c1iscaux/testScripts/testWhtGain_190926.py 

Whitening #1: No issue found.

Whitening #2: No issue found. Some of the step plots showed truncation of the data at the end. But this is an artifact of cds.getdat. The striptool show nothing irregular.

Whitening #3: POP110Q and the spare channel (CH8) did not show the reaction. REFL33Q showed some systematic gain deviation. It could just be the offset problem, but needs to be rechecked.

Whitening #4: The DC channels were found to be OK  except for ASDC. ASDC shows earlier saturation. The input was lowered to 5mVDC to avoid saturation in the second trial. The circuit needs to be checked. The spare channels look noisy, but this is because there is no way to turn off the whitening filters for them.


- AA Filter Test

Injected 11kHz 1Vpp sine wave to the whitening filters. The whiter gains were kept at 0dB. If the AA is disabled, the alias of the 11kHz signal appears in the time series.
-> Whitening #1, #3 and #4: the enable/disable worked correctly.
-> Whitening #2 AA
Bbypass no effect. this is an expected behavior.
 

Attachment 1: Wht1.pdf  183 kB  Uploaded Fri Sep 27 03:39:22 2019  | Hide | Hide all
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Attachment 2: Wht2.pdf  195 kB  Uploaded Fri Sep 27 03:39:22 2019  | Hide | Hide all
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Attachment 3: Wht3.pdf  223 kB  Uploaded Fri Sep 27 03:39:22 2019  | Hide | Hide all
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Attachment 4: Wht4.pdf  292 kB  Uploaded Fri Sep 27 03:39:22 2019  | Hide | Hide all
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Attachment 5: lock.png  11 kB  Uploaded Fri Sep 27 03:39:45 2019  | Hide | Hide all
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