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Entry  Tue Jul 16 16:00:01 2019, gautam, Update, CDS, c1iscaux Supermicro setup IMG_7769.JPG
    Reply  Wed Jul 17 21:22:41 2019, gautam, Update, CDS, CM board Latch Enable subtlety 
       Reply  Sun Jul 21 12:55:38 2019, gautam, Update, CDS, CM board Latch Enable test script LatchLogic.pdfLatchLogicTest.png
          Reply  Fri Aug 9 08:59:04 2019, gautam, Update, CDS, Prep for install of c1iscaux 
             Reply  Sun Aug 11 11:47:42 2019, gautam, Update, CDS, Bench test of c1iscaux 
                Reply  Mon Aug 12 17:36:04 2019, gautam, Update, CDS, More bench test of c1iscaux iscauxCheclist.pdf
                   Reply  Mon Aug 12 21:25:19 2019, Koji, Update, CDS, More bench test of c1iscaux 
                   Reply  Tue Aug 13 08:07:09 2019, gautam, Update, CDS, P1--->P2 
                      Reply  Tue Aug 13 14:36:17 2019, gautam, Update, CDS, P1--->P2 
                   Reply  Fri Aug 16 16:40:04 2019, gautam, Update, CDS, 1Y3 work newLook1Y3.JPGIMG_7803.JPGc1lsc_crashed.png
                      Reply  Sat Aug 17 16:49:23 2019, gautam, Update, CDS, More 1Y3 work Screen_Shot_2019-08-17_at_3.00.57_PM.pngScreen_Shot_2019-08-17_at_3.12.23_PM.pngIMG_7804.JPGScreenshot_from_2019-08-17_17-04-47.png
                         Reply  Mon Aug 19 14:36:21 2019, gautam, Update, CDS, c1iscaux remaining work caseForSmallerFootprint.pdf
                            Reply  Tue Aug 20 19:05:24 2019, Koji, Update, CDS, MC1 (and MC3) troubleshoot Screenshot_from_2019-08-20_17-26-01.pngScreenshot_from_2019-08-20_17-43-03.png
                               Reply  Thu Aug 22 12:54:06 2019, Koji, Update, CDS, MC1 glitch removed (for now) and IMC locking recovered 7x
                                  Reply  Thu Aug 22 20:56:51 2019, Koji, Update, CDS, MC1 glitch removed (for now) and IMC locking recovered 
                            Reply  Fri Aug 23 18:46:17 2019, Jon, Update, CDS, c1iscaux remaining work 
                               Reply  Sun Aug 25 14:18:08 2019, gautam, Update, CDS, c1iscaux remaining work Screen_Shot_2019-08-25_at_10.38.37_PM.png
    Reply  Thu Jul 18 10:46:04 2019, gautam, Update, CDS, Database files made 
       Reply  Thu Jul 18 19:58:56 2019, gautam, Update, CDS, Work on Acromag chassis IMG_7771.JPGIMG_7770.JPGIMG_7772.JPG
          Reply  Fri Jul 19 19:44:03 2019, gautam, Update, CDS, Database file test Whitening.png
Message ID: 14841     Entry time: Mon Aug 12 17:36:04 2019     In reply to: 14840     Reply to this: 14843   14844   14848
Author: gautam 
Type: Update 
Category: CDS 
Subject: More bench test of c1iscaux 

[chub, gautam]

With Chub's help, most of the problems have been resolved. Summary: I judge that we are good to go ahead with an install tomorrow.

  1. The problem with the BIO channels was a mis-wiring internal to the chassis - Chub fixed this and now all 32 AA enable/disable switches seem to work as advertised. Of course we will need to do the in-situ test to make sure.
  2. The problem with the ADC channels were multiple:
    • On the software end, I had gotten some addressing wrong - this was fixed.
    • On the hardware side - even though the inputs of the Acromag are "differential", I found that the readback was extremely noisy (~0.5 V RMS for a 3 V DC signal from the handheld calibrator unit 😲 ). Looking through the manual, I found a recommendation (pg10) that the "IN-" terminal of the Acromag ADC units be tied to the "RTN" pins on the same units. I don't know if this preserves the differential receiving capability of the Acromag ADCs - anyways, after Chub implemented this change, all the Analog Input channels behave as expected (I tested with a DC voltage and also a 200 mHz sine wave from a function generator).
    • Note that most of the Eurocard electronics we use are single-ended sending anyways.
    • What does this mean for the other Acromag ADCs (e.g. OSEM Shadow Sensor monitors) we have installed????? I saw no documentation in the elog/wiki.
  3. Binary input channel:
    • This is used by the "CM LIMIT" channel.
    • I found that I had to initialize a separate alias for the BIO3 unit, which acquires this signal, to use the modbus function "4" corresponding to "Read Input Registers" - c.f. the binary output modbus function 6, which is to "Write Single Register".
    • The fix for the mbbo channels is also likely to be along this lines - but I don't have the energy for that endavor right now.
  4. Testing of the physical mbboDirect bit channels using the Acromag Window utility
    • I can't get the mbboDirect EPICS record to work as expected, so I decided to use the native Acromag utility to test the functionality
    • First I released control of the acromags from the supermicro (stopped modbus)
    • There were several wiring errors - Chub had left for the day so I just fixed it myself.
    • The LED tester kit was used to check that the correct bits were flipped - they were.
  5. At the time of writing, the non-functional channels (in EPICS) are all related to the CM board:
    • C1:LSC-CM_LIMIT (binary input) tested later in the day, works okay...
    • C1:LSC-CM_REFL1_BITS (mbboDirect)
    • C1:LSC-CM_REFL2_BITS (mbboDirect)
    • C1:LSC-CM_AO_BITS (mbboDirect)
    • C1:LSC-CM_BOOST2_BITS (mbboDirect)

Since we don't immediately need the CM board, I say we push ahead with the install - at least that will restore the ability to lock PRMI / DRMI. Then we can debug these issues in situ - I'm certain the issue is related to the EPICS/Modbus setup and not the hardware because I verified the physical channel map using the Acromag windows utility.

Remaining Tasks:

  1. Install power supply cables at 1Y3
  2. Install supermicro and Acromag crates in 1Y3
  3. Migrate existing P1 connectors to P2 where applicable (Whitening boards)
  4. Connect Dsub-->P1 / P2 adaptors
  5. Run in-situ tests
Quote:

I bench tested the functionality of all the c1iscaux Acromag crate channels. Summary: we are not ready for a Monday install, much debugging remains.

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