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Entry  Mon Jul 14 13:03:23 2014, Akhil, Summary, Electronics, Timing Issues of Mini Circuits UFC-6000: Solved 0.2timinganalysis.png0.3timinganalysis.png0.5timinganalysis.png1stiminganalysis.pngpdf.zip
    Reply  Mon Jul 14 14:28:27 2014, Koji, Summary, Electronics, Timing Issues of Mini Circuits UFC-6000: Solved 
    Reply  Tue Jul 15 01:31:13 2014, Akhil, Summary, Electronics, Timing Issues of Mini Circuits UFC-6000: Solved qnoise.pngqnoise.pdf
Message ID: 10193     Entry time: Mon Jul 14 13:03:23 2014     Reply to this: 10194   10199
Author: Akhil 
Type: Summary 
Category: Electronics 
Subject: Timing Issues of Mini Circuits UFC-6000: Solved 

Main Problem:

The frequency counter (FC) takes in an analog RF input(signal) and outputs the frequency of the signal(Ranging from 1 MHz- 6000 MHz) in the digital domain (into a processor). The FC samples the data with a given sample rate( user defined) which ranges from 0.1 s to 1 s(faced problems in fixing this initially).  For data acquisition, we have been using a Raspberry Pi(as a processor) which is connected to the martian network and can communicate with the computers inside the 40m.  The ultimate challenge which I faced( and been knocking my head off from past two-three weeks) is the synchronization of clocks between the Raspberry Pi and the FC i.e the clock which the FC uses to sample and dump data( every 'x' s) and the clock inside the raspberry pi( used  in the loop to wait for a particular amount of time the frequency counter takes to dump successive data).


Steps Taken:

  • To address this problem, first I added an external clock circuit which monitors the Raspberry Pi and the FC to dump and read data at a particular rate(which is equal to the sampling rate of the FC)In detail: http://nodus.ligo.caltech.edu:8080/40m/10129. 
  • While doing so, at first the level trigger algorithm was used which means that the external clock frequency was half as that of  the reciprocal of the sampling rate and a trigger was seen every time the level shifts from +DC to -DC(of the external square wave).
  • But this did not completely mitigate the issues and there were still few issues on how quickly the ADC reads the signal and R Pi processes it.
  • To minimize these issues completely, an edge trigger algorithm which detects a pos edge(rising)  of the clock was used. The clock  frequency is now equal to the reciprocal of the sampling rate. This algorithm showed better results and greatly minimized the drift of the sampling time.

Psuedo Code(code attached):

open device : FC via USB-HID;

open device : ADC via I2C;

always(for t= recording time):

            read data from ADC(external clock);

            if pos edge detected:

                    read data from FC and store it in a register;

             else read data from ADC;


write data stored in the register to a file( can be an Epics channel or a text file);



The attached are the plots showing the time between samples for a large number of samples taken for different sampling times of the FC. The percentage error is the percentage of standard error in the timing between two samples for the data for the entire measurement. It can be inferred that this error has been cut down to the order of ms.


To do next:

  • I have started taking phase measurements( analysis and plots will follow this elog) and also the PSD plots with the improved timing characteristics.






Attachment 1: 0.2timinganalysis.png  12 kB  Uploaded Mon Jul 14 15:19:28 2014  | Hide | Hide all
Attachment 2: 0.3timinganalysis.png  13 kB  Uploaded Mon Jul 14 15:19:43 2014  | Hide | Hide all
Attachment 3: 0.5timinganalysis.png  11 kB  Uploaded Mon Jul 14 15:20:02 2014  | Hide | Hide all
Attachment 4: 1stiminganalysis.png  14 kB  Uploaded Mon Jul 14 15:20:27 2014  | Hide | Hide all
Attachment 5: pdf.zip  85 kB  Uploaded Mon Jul 14 15:22:14 2014
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