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Message ID: 10151     Entry time: Tue Jul 8 09:02:02 2014
Author: Akhil 
Type: Update 
Category: Electronics 
Subject: PSD Plots for different sampling times of the Frequency Counter 

 Although there were few timing issues with the FC and the Raspberry Pi at the lowest sampling time of the FC (0.1s) even after adding an external trigger circuit, it turned out that most of these issues are not prevalent at higher sampling times(>0.5 s)(narrow peaks of PSD seen for higher sampling times). Rana suggested me to look at the PSD plots at different sampling times of the FC so that we can decide which would be the optimal sampling time to work with the FC before replacing the spectrum analyzer. I took the measurements with the setup discussed in my previous elog(http://nodus.ligo.caltech.edu:8080/40m/10129) . However, the  noise of the R Pi- FC interface should be taken care of (I will discuss it with my mentors).

Attached are the plots at 100 MHz carrier frequency at  different sampling times of the FC( 0.1s, 0.2s, 0.3s, 0.5s, 1s) (pdfs and code attached in a zip file)

RXA: Put all the plots in a single PDF file and use the same axis limits for all plots so that its easy to compare.      (Attached in PSD.pdf)


 

 

Attachment 1: 0.1s.png  12 kB  | Hide | Hide all
0.1s.png
Attachment 2: 0.2s.png  12 kB  | Hide | Hide all
0.2s.png
Attachment 3: 0.3s.png  12 kB  | Hide | Hide all
0.3s.png
Attachment 4: 0.5s.png  12 kB  | Hide | Hide all
0.5s.png
Attachment 5: 1s.png  9 kB  | Hide | Hide all
1s.png
Attachment 6: Pdf.zip  26 kB
Attachment 7: PSD.pdf  17 kB  Uploaded Wed Jul 9 12:10:10 2014  | Hide | Hide all
PSD.pdf
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