Finally, the 0.1s sampling rate of the frequency counter(FC) has been achieved. For this I had to :

 Send in byte codes to set a particular range of the frequency counter.

I was digging  in to find how exactly the circuit inside the frequency counter works and how the processor inside is able to read and write bytes through a HID-USB interface. I found out that the 'AutoRange' setting (which I have been using so far) has an independent  multiplexing circuit  which consumes some time(that varies with the drift in frequencies) and thus, the the processor waits for some specific time for this process and cannot reach the minimum 0.1 s sampling time. To mitigate this issue, I set the range bytes to the appropriate range of frequencies so that I can bypass the MUX  delay. Here is the list of Range and frequencies for the FC:

Range 1:    1 - 40 MHz

Range 2:    40 - 190 MHz

Range 3:    190 - 1400 MHz

Range 4 :   1400 - 6000 MHz

I then took measurements for sampling time of 0.1 s at carrier frequencies of 5 MHz and 25 MHz from SRS DS345  and plotted the improvised gain plots(attached) to those in my previous elog(10070)  with the same procedure mentioned before.

To do Next:

Plot the gain plots for higher carrier frequencies till range 3 using Marconi Function generator.

Write the data from FC into C1: ALS-Y_SLOW_SERVO1_OFFSET EPICS channel.